This application claims priority to Korean Patent Application No. 2000-67773 filed on Nov. 15, 2000, and Korean Patent Application No. 2001-27287 filed on May 18, 2001, the contents of both of which are herein incorporated by reference in their entirety.
The invention relates to a data processing system, and more particularly to a data processing system having a data output buffer that can be used as both a peripheral component interconnect (PCI) buffer and a peripheral component interconnect extended (PCI-X) buffer.
It is common for personal computers or work station systems to be equipped with a PCI bus for data transmission between components.
A PCI bus must comply with different operating standards for its buffer in accordance with different signal voltage environments. For example, a PCI bus buffer must comply with a maximum data transfer rate of 533 MB/sec at an operational frequency of 66 MHz in a 3.3V signal voltage environment, and a maximum data transfer rate of 133 MB/sec at an operational frequency of 33 MHz in a 5V signal voltage environment.
FIG. 1 is a schematic block diagram, which illustrates a conventional PCI buffer. Referring to FIG. 1, the PCI buffer 10 should have different driving capacities according to the level of an input signal voltage. Specifically, the driving capacity for a 5V input signal voltage should differ from that for a 3.3 V input signal voltage. A driving capacity control circuit 12 of the PCI buffer 10 functions to control the driving capacities with respect to the input signal voltage. However, because the conventional driving capacity control circuit 12 has no voltage level discriminator, it should be externally provided with a signal for discriminating the voltage level.
A PCI-X bus specification has been proposed that is derived from the PCI bus specification. According to the specification, it is required that a PCI-X bus meet a maximum data transfer rate of 1,033 MB/sec at an operational frequency of 133 MHz in the voltage environment of 3.3V.
Until now, there exists no data output buffer that can be used as both a PCI-X buffer and a PCI buffer.
It is an object of the invention to provide an improved data processing system having a data output buffer that can be used as both a PCI buffer and a PCI-X buffer.
It is another object of the invention to provide a data processing system having a voltage level discriminator so as to control signal driving capacities according to an input voltage level.
Disclosed is a data processing system comprising a control unit for receiving data from a main core and outputting given control signals, a level shifter for amplifying the electric potential of said given control signals and outputting corresponding driving signals, a data output buffer for receiving said driving signals from said level shifter and outputting a driving voltage having a voltage range defined in the PCI or/and PCI-X specifications, to an input/output pad, and said data output buffer being in a high impedance state to prevent a PCI mode voltage inputted to said pad from being leaked to a power source terminal when said data processing system is operated in PCI mode.
In another aspect of the invention, said data output buffer comprises a pull-up transistor having one end connected to a power source terminal, a first resister coupled between said pad and the other end of said pull-up transistor for controlling a current flowing from said power source terminal to said pad to have a current range that complies with the PCI and PCI-X specifications, a second resister having one end connected to said pad, for controlling a current flowing from said pad to a ground terminal to have a current range that complies with the PCI and PCI-X specifications, a pull-down transistor having one end connected to said ground terminal, a pull-down transistor protection unit coupled between the other end of said second resister and the other end of said pull-down transistor, for controlling said pull-down transistor to make an electric potential of said other end of said pull-down transistor to come to VDD (power source voltage)xe2x80x94VTH (threshold voltage of said pull-down transistor protection unit) in said PCI mode, a leak prevention unit coupled between said pad and a gate of said pull-up transistor, for controlling said pull-up transistor to prevent said current from being leaked from said pad to said power source terminal in said PCI mode, and a pass transistor coupled between said power source terminal and said pad, for passing said driving signals generated from said level shifter, to said gate of said pull-up transistor.
In another aspect of the invention, said pull-up transistor is formed of a PMOS type transistor having a bulk terminal connected to an input voltage to which a voltage of 3.3 or 5V is supplied in said PCI or PCI-X mode.
In another aspect of the invention, said pull-down transistor is formed of a NMOS type transistor.
In another aspect of the invention, said pull-down transistor protection unit is formed of a NMOS type transistor.
In another aspect of the invention, said leak prevention unit is formed of a PMOS type transistor having a bulk terminal connected to an input voltage to which a voltage of 3.3 or 5V is supplied in said PCI or PCI-X mode.
In another aspect of the invention, a voltage of 3.3V is supplied to said power source terminal connected with said one end of said pull-up transistor.
In another aspect of the invention, a voltage of 3.3V is supplied to said power source terminal connected with said gate terminal of said NMOS transistor.
In another aspect of the invention, a voltage of 3.3V is supplied to said power source terminal connected with said gate terminal of said PMOS transistor.
In another aspect of the invention, said control unit includes a voltage level discriminator for discriminating a level of said input voltage inputted from outside to output a discrimination signal, and said data output buffer controls the driving capacity thereof in response to a control signal outputted from said level shifter according to said discrimination signal.
In another aspect of the invention, said data output buffer includes subsidiary pull-up and pull-down transistors to control the driving capacity thereof in response to said control signal corresponding to said discrimination signal.
In another aspect of the invention, said voltage level discriminator comprises a comparative circuit for comparing said input voltage inputted from outside with a standard voltage to output a comparative signal, and a latch circuit for latching said comparative signal.
In another aspect of the invention, said comparative circuit comprises a first voltage distribution circuit for distributing said input voltage to output a first voltage, a second voltage distribution circuit for distributing an power source voltage to output said standard voltage, and a comparator having a non-converted input terminal for receiving said first voltage, a converted input terminal for receiving said standard voltage, and an output terminal for outputting said comparative signal.
In another aspect of the invention, said first voltage distribution circuit comprises a NMOS transistor having a first current electrode, a control electrode connected with a control signal that is activated when said power source voltage is supplied, and a second current electrode connected with a ground voltage, at least two resistors connected in series between said input voltage and said first current electrode of said NMOS transistor, and wherein said first voltage is outputted from one of connecting nodes of said resistors of said first voltage distribution circuit.
In another aspect of the invention, said second voltage distribution circuit comprises a NMOS transistor having a first current electrode, a control electrode connected with said control signal that is activated when said power source voltage is supplied, and a second current electrode connected with said ground voltage, at least two resistors connected in series between said power source voltage and said first current electrode of said NMOS transistor, and wherein said standard voltage is outputted from one of connecting nodes of said resistors of said second voltage distribution circuit.
In another aspect of the invention, said latch circuit is synchronized with a converted signal of said control signal that is activated when said power source voltage is supplied, to latch said comparative signal outputted from said comparator.
Disclosed is a data processing system comprising a control unit for receiving data from a main core and outputting given control signals, having a voltage level discriminator for discriminating a level of an input voltage inputted from outside to output a discrimination signal, and a data output buffer for outputting a driving voltage to an input/output pad in response to the control signals and controlling the driving capacity in response to the discrimination signal.
In another aspect of the invention, said voltage level discriminator comprises a comparative circuit for comparing said input voltage inputted from outside with a standard voltage to output a comparative signal, and a latch circuit for latching said comparative signal.
In another aspect of the invention, said comparative circuit comprises a first voltage distribution circuit for distributing said input voltage to output a first voltage, a second voltage distribution circuit for distributing an power source voltage to output said standard voltage, and a comparator having a non-converted input terminal for receiving said first voltage, a converted input terminal for receiving said standard voltage, and an output terminal for outputting said comparative signal.
In another aspect of the invention, said first voltage distribution circuit comprises a NMOS transistor having a first current electrode, a control electrode connected with a control signal that is activated when said power source voltage is supplied, and a second current electrode connected with a ground voltage, at least two resistors connected in series between said input voltage and said first current electrode of said NMOS transistor, and wherein said first voltage is outputted from one of connecting nodes of said resistors of said first voltage distribution circuit.
In another aspect of the invention, said second voltage distribution circuit comprises a NMOS transistor having a first current electrode, a control electrode connected with said control signal that is activated when said power source voltage is supplied, and a second current electrode connected with said ground voltage, at least two resistors connected in series between said power source voltage and said first current electrode of said NMOS transistor, and wherein said standard voltage is outputted from one of connecting nodes of said resistors of said second voltage distribution circuit.
In another aspect of the invention, said latch circuit is synchronized with a converted signal of said control signal that is activated when said power source voltage is supplied, to latch said comparative signal outputted from said comparator.
Disclosed is a data processing system comprising means for receiving data from a main core and outputting given control signals, means for amplifying the electric potential of said given control signals and outputting corresponding driving signals, buffer means for receiving said driving signals from said level shifter and outputting a driving voltage having a voltage range defined in the PCI or/and PCI-X specifications, to an input/output pad, and said buffer means being in a high impedance state to prevent a PCI mode voltage inputted to said pad from being leaked to a power source terminal when said data processing system is operated in PCI mode, and wherein said buffer means further comprises a pull-up transistor having one end connected to a power source terminal, means for controlling a current flowing from said power source terminal to said pad to have a current range that complies with the PCI and PCI-X specifications, a second resister having one end connected to said pad, for controlling a current flowing from said pad to a ground terminal to have a current range that complies with the PCI and PCI-X specifications, a pull-down transistor having one end connected to said ground terminal, means for controlling said pull-down transistor to make an electric potential of said other end of said pull-down transistor to come to VDD (power source voltage)xe2x80x94VTH (threshold voltage of said pull-down transistor protection unit) in said PCI mode, means for controlling said pull-up transistor to prevent said current from being leaked from said pad to said power source terminal in said PCI mode, and means for passing said driving signals generated from said level shifter, to said gate of said pull-up transistor.